- UID
- 5262
- 斋米
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- 斋豆
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- 回帖
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- 积分
- 101
- 在线时间
- 小时
- 注册时间
- 2010-10-7
- 最后登录
- 1970-1-1
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Intern positions:
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3 O# Q' _7 P. Y) k$ p: X9 _+ {7 zASIC Design/Verification Intern (Vacancy:3)
$ w9 ]; q5 T3 y# e& t5 jJob Description:
' ~8 I! y6 E6 ^3 @" r1. Design/Verification of video surveillance and audio & voice processor with integrated CODEC and amplifier- {( u2 \8 p: X, r! A3 t* i
2. Unit level & system level testbench build up with SystemC or OVM/UVM$ U' a! L7 i& ^& f% J0 _
3. Bus Functional Models & APIs development! O& @0 |( O3 s3 r. y5 X
4. Verification of AMBA-based DMA, DDR Memory Subsystem, and peripheral interfaces including PCIe, USB, SPI, BT656/BT1120, I2C, etc.7 n9 ~5 ^6 j0 j0 s
5. High-quality verification with Code Coverage analysis and functional coverage analysis
1 G6 d, X. M# ]9 z7 y( p; u4 a6. Provide support to ATE/DFT and Validation7 S$ ^* G1 F3 A2 q- ~- V- k t
- I8 M+ n& o; G6 B5 QJob requirement: ! ^8 d. w& x+ ~+ O# o0 q* u; z
1. Majoring in Electrical Engineering, microelectronics or image/graphics processing is preferred5 j3 `' | m6 s
2. Master C/C++ coding and verilog coding, systemC and SystemVerilog is preferred, w* K6 Y$ }- Q4 W- Y
3. Strong DSP background is highly desirable, V9 z! O. ^ h, ?' E
4. Knowledge of video coding standard including H264 MPEG-4 is preferable.
' H. F) A: K- v, B% l+ F5. Knowledge of RTL design and verification4 \% d1 z. W* b6 b6 I0 V$ p
6. Knowledge of Perl and Tcl scripting
/ U6 Z) o- I8 {2 V& e7. Able to understand Verilog RTL code, debug simulation errors, identify and fix RTL/Environment issues
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联系人:# ]% M/ g# d; w3 f
卢先生# ^9 A2 M3 c1 O8 X% R) G
邮箱:lush123@sina.com, ?8 S @# [+ s
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