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Intern positions:6 g: }/ P2 [2 T6 Z
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ASIC Design/Verification Intern (Vacancy:3). {8 w& s3 a# A, e! V, J
Job Description:
7 y. a) n. X' V1. Design/Verification of video surveillance and audio & voice processor with integrated CODEC and amplifier9 r5 x6 u4 t" m! P
2. Unit level & system level testbench build up with SystemC or OVM/UVM7 p1 |# u2 Q( T* W6 W
3. Bus Functional Models & APIs development! ^0 O7 x9 F7 g' n
4. Verification of AMBA-based DMA, DDR Memory Subsystem, and peripheral interfaces including PCIe, USB, SPI, BT656/BT1120, I2C, etc.5 h9 n5 {( Z4 m8 e# z- c! O
5. High-quality verification with Code Coverage analysis and functional coverage analysis$ V2 @" ?7 z R- Q. P
6. Provide support to ATE/DFT and Validation& ]7 q/ F# x1 i t* l' z4 L3 ^
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Job requirement: ( z# m' p8 q1 Z' ?
1. Majoring in Electrical Engineering, microelectronics or image/graphics processing is preferred
( y/ L' \2 m& R$ l: @8 t, ^2. Master C/C++ coding and verilog coding, systemC and SystemVerilog is preferred7 |: u" [6 C2 G8 x4 X
3. Strong DSP background is highly desirable8 c; @) o0 I. A( \9 X
4. Knowledge of video coding standard including H264 MPEG-4 is preferable.
' K7 I6 j S* L# B; K6 ]& X5. Knowledge of RTL design and verification+ L9 o4 H. w. S: a1 Y3 H0 u# |
6. Knowledge of Perl and Tcl scripting
! g) y6 g/ e; G* {2 q7. Able to understand Verilog RTL code, debug simulation errors, identify and fix RTL/Environment issues
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: M( {+ E+ ?$ P* q. D联系人:8 g! X* d, W" A# p! S9 a
卢先生' w0 O- B6 |1 b4 r" L& ^7 c
邮箱:lush123@sina.com
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