Conexant 成都公司实习招聘

zl182005

Conexant  chengdu
公司要招聘如下岗位的实习生
5 W9 z% q' ~4 i7 u& v' @Intern positions:
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ASIC Design/Verification Intern (Vacancy:3)

/ g) l6 T- }2 Z1 |5 B$ k* _- L! PJob Description:
! q# z  {7 ?& M, A) r/ B8 V1. Design/Verification of video surveillance and audio & voice processor with integrated CODEC and amplifier
2. Unit level & system level testbench build up with SystemC or OVM/UVM
! ~( k5 P$ Y  P6 S' c) _3. Bus Functional Models & APIs development
8 t# d  e" B6 R& b2 s* y8 `4. Verification of AMBA-based DMA, DDR Memory Subsystem, and peripheral interfaces including PCIe, USB, SPI, BT656/BT1120, I2C, etc.
3 v( `* t; N5 z0 V/ L3 s8 }' O5. High-quality verification with Code Coverage analysis and functional coverage analysis
6. Provide support to ATE/DFT and Validation

Job requirement:
: Y& [- i; I" j8 _  ^1. Majoring in Electrical Engineering, microelectronics or image/graphics processing is preferred
2. Master C/C++ coding and verilog coding, systemC and SystemVerilog is preferred
4 L0 e1 _8 D  o) h4 m, C6 G  ~3. Strong DSP background is highly desirable
0 r+ k( ]; G) f* D4. Knowledge of video coding standard including H264 MPEG-4 is preferable.
! O6 i. ?' R( y5. Knowledge of RTL design and verification
% {; Q& z$ H; p# \9 X* p. |6. Knowledge of Perl and Tcl scripting
# M5 M/ O/ w1 Q: T7. Able to understand Verilog RTL code, debug simulation errors, identify and fix RTL/Environment issues

/ g$ Z& |% l( d* I* _Job requirement:
1. Majoring in Electrical Engineering, microelectronics or image/graphics processing is preferred
! ]/ w" X1 }$ V. m) r2. Master matlab is preferred
( `' V; Y8 y) w4 I  Y1 I8 a) O$ g, C3. Master digital signal process
4. Master Runge-Kutta and math analysis

联系人：
4 e; `4 _4 k5 p5 c( h卢先生
请投简历至 邮箱：lush123@sina.com
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! z- O% `) B+ t6 t. ^可以2500/月以上

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