Conexant 成都公司招聘

zl182005

Chengdu Conexant Regular Full-time positions:

SoC ASIC Design/Verification Engineer( Vacancy:1)

, f2 N% ~* U- E$ o; [6 J, h& vJob Responsibilities:
1. Integration of ARM processor/DSP co-processor and AMBA bus for SoC;
/ Q  }) o6 p* l& T  V5 [, ^  o* A6 M2. Integration of H264 Codec , DDR, USB and PCIe etc for SoC;
( D7 O/ }  S% O3. Design erification of video surveillance and audio & voice processor with integrated CODEC and amplifier
4. Design SoC-level logic including clock, reset, and DFT;
1 A% ?# |* _5 t% q8 ^: l5. Verification of AMBA-based DMA, Memory Subsystem, and all peripheral interfaces at unit level and SoC level
6. Work with analog group and physical layout team on analog macro integration and synthesis/timing analysis.

8 C& w' ~' C2 A* WJob Requirements:
1. 5+ years experience on SoC design and integration;
2. Hand-on experience in ASIC flow;
3. Experience of ARM/DSP/AMBA integration and/or verification;
4. Experience of DMA design and/or verification;
. S' \6 `( a: Q9 U+ y5. Experience of H264 Codec & DDR SoC integration and verification
6. Experience of video surveillance project design and verification
7. Experience of design erification for audio & voice processor with integrated Codec and amplifiers is a big plus
& `' y2 O4 J- f- b. I8. Domain knowledge on Nand Flash Controller, USB, and PCIe is a plus
- F/ v6 k4 C5 M' T: [. u8 s9. DFT (Memory BIST and scan) design background is a plus

5 k. y1 @6 s) |  r# {5 MASIC Verification Engineer( Vacancy:2)
% @! h) j+ Z5 B0 C2 f& W" N" o; z
Job Description:
1. Instrumental in the development of infrastructure for the validation of OVM/UVM-based architectures and the verification of ASIC hardware.
2. Additional duties include the development of directed and random hardware verification environments, and the application of those environments to ASIC verification
& z8 G0 P! r% u5 \$ h. o( e3. Integration of VIP and functional verification agents in OVM/UVM verification environment to support coverage-driven verification
4. Understand and verify the functionality of a given design element within the context of the block, chip and overall system
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$ @2 l3 T$ Q7 m& O/ I0 BJob Requirements:
1. Extensive Verilog experience with SOC verification environments.
2. Verification experience on digital signal processing for communication system.
( R& E2 C4 Y  Q4 V$ A# d/ v9 L3. Experience developing bus functional models, monitors, scoreboards, generators, functional coverage models
4. Experience with high level verification languages such as SystemC, SystemVerilog, OVM or VMM, Vera or Specman, and strong C++ programming background
5. Shell scripts and Tcl/Perl expertise, create runsim, lsf, regression management scripts
2 N0 c: b6 I! S- y4 g# Q+ g6. Able to understand Verilog RTL code, debug simulation errors, identify and fix RTL/Environment issues
' m: {4 f/ B3 {6 r2 }+ z& n. I3 E7 k7. Strong DSP background is highly desirable
8. Experience on SD/HD/SDI video is a plus
! _( c3 ]5 [: T; C9. H264 Codec design erification experienced is desired
, D0 p9 G9 q6 V  }5 d10. Experience of design erification for cable equalizer is preferred
2 R/ h. W9 f) F. {9 ]5 y
  C6 o7 p- \* B0 m/ t6 IInter Algrithom Engineer( Vacancy:2)
Job requirement:
1. Majoring in Electrical Engineering, microelectronics or image/graphics processing is preferred
8 X  u& l* w8 Q  `2. Master matlab is preferred
3. Master digital signal process or Opencv
( K" w; y2 a) e4. Master and math analysis


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