【实习】NVIDIA 英伟达实习生招聘！！！

nvidiahr

有兴趣的同学，将简历投递至harryf@nvidia.com 所有职位都是base在上海
_________________________________________________________________________
ASIC Intern

! z/ i/ v$ U+ U: N& mJob Description/Qualifications:
- e! s8 [; r3 N1 x( E0 I: D- BS/MS in electrical/computer engineering and related.
- Good skills in Verilog. Solid understanding in RTL sim verification of digital design.
9 V. o/ t& C$ X9 U- Perl scripting skills is appreciated as a plus.
- Fluent English (both written and spoken) and excellent communication skills
- Demonstrated ability to work independently as well as in a multi-disciplinary group environment
6 F/ u6 h4 e% M) |8 ?______________________________________________________________________________
$ \6 R2 _' A' Q7 uASIC design/verification intern
. F) M  ~3 f! r
- {! A1 Y: F/ V4 B2 v; L8 ^4 ZJob Description/Qualifications:
- BS/MS in electrical/computer engineering and related.
- Good skills in Verilog. Solid understanding in RTL sim verification of digital design.
" ?' N+ `( ~/ l, \" c$ P) R- Perl scripting skills is appreciated as a plus.
- Database/Web design experience is appreciated as strong plus.
0 K. S" T7 U) i- Fluent English (both written and spoken) and excellent communication skills
) ?9 r' b8 S% s) J- Demonstrated ability to work independently as well as in a multi-disciplinary group environment
. p# A( g( F" d& N& r0 x______________________________________________________________________________
. C/ b' s2 R" P) W1 c. j1 v; s1 ~ASIC Intern
8 u' H( N0 v9 @& J/ T. u
- e# E( B# j+ m5 eJob Description/Qualifications:
+ y5 W. ^3 j9 x8 e8 @- Maintain regression suit, triage failing tests
- Improve wiki page and user documents
- Maintain infrastructure and tree
& V8 h7 t. ]: `7 r4 n$ T/ B______________________________________________________________________________
3 f2 K9 ~4 Z( w5 z% Y* |' cPhysical Design Engineer
Responsible for flow automation, regression test.
6 ~0 y4 K) s2 UAnalysis on placement, routing, timing, clock, power, noise and DFM.
On-demand testing support and infrastructure coding in perl/tcl/makefile/java.

9 Z4 H- C$ h8 jMinimum Requirement:
. s: A- ~: A7 J. s) S8 F, K# ~7 \MSEE
, z6 V* ^+ i3 H* W: g5 b/ c' oBasic knowledge of device model, processing technology, timing, noise and power in chip design.
Proficient user of Perl or TCL ( or C, Python) is preferred.
Hands-on experience in EDA software from Synopsys (PC/ICC/DC/PT/STAR-RC), Cadence (First Encounter) is a plus.
6 X. o5 e9 i* j% F  n9 [___________________________________________________________________________
System Design Engineer - GPU Arch

$ x; \) X# b" B, b- n8 UJob Description/Qualifications:
Responsibilities:
- We are looking for world class engineers to design, model, analyze and verify next generations of GPU architecture.
" `+ _/ D# }! [1 h+ K- The candidates will work with a group of architects to design and develop proprietary internal tools for the visualization, analysis, and debug and verification of tests and applications on various functional and performance simulations of future chips.
3 o& p0 q3 V5 A. j4 r3 Y1 ]' I- The candidates will have opportunities to get involved in cutting-edge GPU macro- and micro-architecture design, verification and optimization, including porting commercial applications to test benches, identifying performance hotspots and data mining for performance analysis.

* L- w$ w. f9 j4 FRequirements:
- Bachelor Degree or higher majoring in CS/EE/Mathematics or relevant fields.
; [9 ^6 p6 ~, y2 \) D& Y! {- Solid computer science background
/ ]+ I0 V; _! u& @+ M- Strong C/C++ programming ability.
- Excellent English writing for engineering documentation, English oral well enough to attend meetings.
- Experience in the following areas is a plus:
- Scripting language (Perl, Python, Ruby) experience is a plus.
* U% y- E# Y0 ^* z; t- 3D graphics (D3D or OpenGL) application development.
0 M7 w9 q# g( V; x# j- Parallel computing/CUDA/OpenCL/HPC development.
- Microprocessor architecture design & verification.
8 u! k, i8 ?& c- System level programming experience in OS, compiler, driver, tools, virtual memory system, etc.
. G4 y1 o: J7 u' \. l; D- Multimedia (video, image processing, visualization) application development
____________________________________________________________________________
Developer Tools QA software  engineer

: w6 y, e- c5 x; t+ p$ UJob Description/Qualifications:
  s" @, q1 a5 [" v- [Qualifications: The candidate will take the responsibility to test our software distributions that includes mobile/embedded OS, SDK, compilers and samples codes.
' @- l" j; A( a- x
) J: u5 u! R" c" p6 `* X- Strong knowledge on Windows and Linux Operating systems
7 `# Z$ e; ?! g7 f, l' ?- Knowledge on build tools like Make and ant
- Strong at scripting, like perl , shell and batch scripting.
8 Y; p+ b- q0 w0 x6 ^. J7 a- Good debugging skills and analysis skills on installations and builds
' m7 r. c9 S% A1 m- Good hands on about Strong analysis skills on system / product configurations and setups.
, W. X7 t/ Y3 b8 n& h& W+ V! J% h- Added advantage with C,C++
___________________________________________________________________________
) i# v' q) \: A6 I6 d
2 A0 Q) x+ i, Y1 u+ CPower ASIC Engineer Intern
, Y0 r: W9 _$ `1 h5 U. U
Power methodology team is responsible for researching power expenditures and workload efficiency to identify architectural, micro-architectural strategies to improve power efficiency of the next generation GPU and TEGRA chips.

# c! ]  J0 l' B3 jResponsibilities:
Develop the power flow to automate the power expenditures measurement.
  u: C( u) J: e/ `2 J9 P8 `" J9 q% `Evaluate new low-power technologies and provide feedback to power ARCH team to improve chip power efficiency on architectural level.
Support GPU/TEGRA RTL designers using the power flow to do the power scrubbing work and improve their power efficiency on micro-arch level.
. F) {! ~: q. k! Q0 hUnderstand and perform block level and chip-level power analysis.

1 M8 j1 C  M5 K/ B& y* |% ]8 \/ D# tRequirements:
Experience on ASIC related areas like ASIC design/verification.
* G" v/ A: b' \& x  WKnowledge on advanced low power techniques and high speed clocking desired.
$ m$ F/ ?- q' {- W- O. R- y$ X! jKnowledge on low power ASIC design/verification.
$ U. c$ ]  m2 \: l- d" h9 PProgramming languages: Strong Verilog (or VHDL), Perl, Tcl is must,  C ++ is a plus.
: c# e; d+ U, A0 U" O4 WTool Familiarity: PTPX, Synopsys Design Compiler, VCS simulation tool is must, Power Artist is a plus.
Excellent communication skills and ability to be good at teamwork.
$ f) \( m0 J/ M( e+ G: ?5 m* XExcellent English writing/speaking skills.
_________________________________________________________________
. Z/ B# `+ F, bCompute Architect Intern
' Y5 H: J. e8 X$ \- b+ V0 e  q! t  vJob Description/Qualifications:
4 x! l' U- G. y+ h/ eThe NVIDIA GPU Computing Architecture group is seeking intern candidates with backgrounds in computer architecture and compute science to join our effort to advance the state of parallel computing.
Our team is designing the fastest and most efficient parallel architectures that power energy-efficient smart phones and the world's fastest super computers.

( i# E5 m" Q  T( O& _4 hRESPONSIBILITIES:
: j) m$ s# v* c9 ~: w7 a; I' }. BDevelop innovative HW, DSP, GPU and system architectures to extend the state of the art in performance, programmability, efficiency and reliability
Analyze and prototype key algorithms for new GPU architectures
  r* R0 L0 B7 K2 }! tCollaborate across the company to guide the direction of GPU computing, working with software, research and product teams

DESIRED SKILLS and EXPERIENCE:
' Z7 h" L: t; TMS Degree in relevant discipline (CS, EE, Math). PhD helpful
Strong programming skills in C or C++
% F; n5 v6 O0 f8 J/ sStrong background in computer architecture, compilers, parallel processing, signal processing and/or high performance computing
(optional) Strong programming skills in CUDA, Perl, OpenMP, MPI or Python is big plus
  w& B  X3 Z( Z- J0 W) O(optional) Experience in computer vision, machine learning, and molecular dynamics is big plus
8 N: I3 p0 o: n- @____________________________________________________________________________________
CUDA AUTOMATION TRIAGE QA ENGINEER

/ `( q' w6 y2 J" IRESPONSIBILITIES:
- GPU Computing test with CUDA to ensure functionality, compatibility and performance.
- Test staging area cuda enabled display driver and CUDA toolkit.
- Report and analyze the nightly failures from CUDA nightly testing.
9 {  ~* o0 a% J% _- Maintain and fix bug for CUDA nightly testing configuration files.
; p' ]2 ]7 i  |7 _  o4 R$ B
8 y+ r5 |$ _. Y% a% P9 }MINIMUM QUALIFICATIONS:
1 F. l; M& l' t0 o) w: N1 s( S4 Y4 ]- A good degree from a leading university in an engineering or computer science related discipline (BS; MS or PhD preferred).
2 {1 V/ I( A; R1 v) d! S& v- Familiar with Linux and Windows operating systems.
- Be good at C/C++ and python programming a plus.
- Good trouble shooting, analytical skill, logical thinking and inferences capability a must.
  k2 x# o% l5 |4 H. Q- Excellent English communication and collaboration skills.
+ R( N4 K4 }; }( U$ ^& }9 z5 |; W- Ability to work independently and achieve results on tight time lines.
, }6 e5 |3 i) P  A2 \2 x+ ~, X
% P& g% v* r; n6 u' I