- UID
- 33999
- 斋米
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- 斋豆
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- 回帖
- 0
- 积分
- 503
- 在线时间
- 小时
- 注册时间
- 2012-9-21
- 最后登录
- 1970-1-1
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Job title : 798200 (XA INT) Post Silicon Validation PCB designer Intern $ W# I; s' r- f9 a+ A5 z, h0 P( }/ S
Location: Xian
8 t# @$ [( s# A# q! k( a8 u- @Position : 1 ! w1 Q/ b7 Q' @0 N9 t: s( [9 D
Contact : fong.ling.loo@intel.com 0 d- _" v: _7 P/ w+ R
Please subject your email as ‘Apply for 798200 (XA INT) Post Silicon Validation PCB designer Intern’ ! g0 B! ]" U- u5 c
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Job Description:
' H6 l6 j N2 o$ ~+ \5 q6 {-Develop the printed circuit board schematic and layout based on post silicon validation team's feature requirement request
! i4 p7 k6 @9 \. D% q5 k' s v2 Q-Handle the BOM and sourcing of components, contacting vendors to confirm the part numbers 3 A) j! H: M3 E! C+ \6 s
-Coordinating PCB production and assembling
4 Q# [6 f. D; I-Bring up the PCB with post silicon validation team members
) t; h# K z$ u-PCB rework and testing
) i" u0 M$ p8 Q! ?& v' B-For all the described jobs scope, there is internal mentor to monitor on quality and guide on right execution steps.
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7 e/ S) u, f2 a% S' eJob Qualifications: . `% D2 X0 j: B1 w
-Knowhow of PCB design is required.
, b$ j. m+ Y+ f9 L+ O# j& ~-Able to read English specifications. . o' X& o& M# F( N
-Existing PCB design experience is a plus.
8 }, X' x O3 B5 L) |* @-Able to read & write English emails.
/ u. X% L! [0 M1 I3 g, F-Spoken English is a plus.
% B6 k" Y1 U( P; r1 ?& X* q4 V-Willing to learn the embedded hardware and software in a flexible and open working environment. * t6 [! T0 t% X& q+ d
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