- UID
- 5262
- 斋米
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- 斋豆
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- 回帖
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- 积分
- 101
- 在线时间
- 小时
- 注册时间
- 2010-10-7
- 最后登录
- 1970-1-1
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Intern positions:
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! B% Y1 q7 H! F6 H8 AASIC Design/Verification Intern (Vacancy:3)
9 m! X. y8 H) \" \! Q' _+ i6 YJob Description:- |- |5 x; e# n6 Q
1. Design/Verification of video surveillance and audio & voice processor with integrated CODEC and amplifier
/ ^; X) Y4 v1 i) k! n2. Unit level & system level testbench build up with SystemC or OVM/UVM! [. {/ x4 K' b4 V0 D& N
3. Bus Functional Models & APIs development
+ b* h4 l7 t* P) @4. Verification of AMBA-based DMA, DDR Memory Subsystem, and peripheral interfaces including PCIe, USB, SPI, BT656/BT1120, I2C, etc." F% k1 ]+ v- Q0 ]- e' B
5. High-quality verification with Code Coverage analysis and functional coverage analysis
% {- K0 s, V/ g4 S6 j# m/ d6. Provide support to ATE/DFT and Validation7 F7 b& ?+ e8 ^- r1 d0 O
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Job requirement: " }" } x+ r8 L" _% e' Q
1. Majoring in Electrical Engineering, microelectronics or image/graphics processing is preferred( R& R9 @6 P( Y: H1 q3 f1 l" l7 c
2. Master C/C++ coding and verilog coding, systemC and SystemVerilog is preferred2 M7 ^5 F! y% A5 q5 ]2 h8 p
3. Strong DSP background is highly desirable
+ s. w) X7 N, X6 i5 [0 ~% @$ [4. Knowledge of video coding standard including H264 MPEG-4 is preferable.8 g1 v; {! _) X; E' g. k
5. Knowledge of RTL design and verification
" v6 d) b- x$ ]# j3 t- @6. Knowledge of Perl and Tcl scripting {! t* P H' |! }0 V
7. Able to understand Verilog RTL code, debug simulation errors, identify and fix RTL/Environment issues
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联系人:2 o: r" i$ Z4 W- x$ n: E1 y
卢先生
! @! C, t! k- Y& u/ V邮箱:lush123@sina.com8 i' i3 I9 e7 V) r
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