- UID
- 5262
- 斋米
-
- 斋豆
-
- 回帖
- 0
- 积分
- 101
- 在线时间
- 小时
- 注册时间
- 2010-10-7
- 最后登录
- 1970-1-1
|
Intern positions:
' \5 M( Q; Z: S9 [6 m' v& t( s
3 e* i* E o4 l n! z5 WASIC Design/Verification Intern (Vacancy:3)8 ?6 |# S4 e1 }! ]
Job Description:
M. W# u$ d; j/ w: M1. Design/Verification of video surveillance and audio & voice processor with integrated CODEC and amplifier
2 v* ]( K) B5 f3 n1 J2. Unit level & system level testbench build up with SystemC or OVM/UVM2 D; e8 u9 h5 ~$ a' p5 H
3. Bus Functional Models & APIs development
7 B& Z# B" Y/ z, {4. Verification of AMBA-based DMA, DDR Memory Subsystem, and peripheral interfaces including PCIe, USB, SPI, BT656/BT1120, I2C, etc.1 b" D! \ h2 \# E1 n
5. High-quality verification with Code Coverage analysis and functional coverage analysis
8 I) ^7 Z" X0 b6 h5 C [% |6. Provide support to ATE/DFT and Validation
; C7 a( |' _8 J0 O' l8 o3 C( `# e0 e( [% V9 d% W- {
Job requirement:
1 w( i$ p; m1 g$ b+ k1. Majoring in Electrical Engineering, microelectronics or image/graphics processing is preferred' e9 {4 a9 s; P
2. Master C/C++ coding and verilog coding, systemC and SystemVerilog is preferred% |1 _9 ?' J& J( d$ ]6 F: u* N
3. Strong DSP background is highly desirable2 b( [% P# p2 W& N
4. Knowledge of video coding standard including H264 MPEG-4 is preferable.; c) W/ y" Z6 d% G9 L" u; c& k2 k4 h
5. Knowledge of RTL design and verification
: s. m. O- h3 n6 R+ s& i. s# _6. Knowledge of Perl and Tcl scripting
' e, C( w9 m) u& `5 m" D7. Able to understand Verilog RTL code, debug simulation errors, identify and fix RTL/Environment issues$ t$ i! r! F+ I: @
7 K! I' x2 o. w$ h7 l3 I5 L& [
联系人:
: {( Y. D- s5 G卢先生
9 h; Z/ j/ k8 c7 a; F$ ?" W; C邮箱:lush123@sina.com9 ?% i1 l9 g: \" G, y. M
|
|