- UID
- 5262
- 斋米
-
- 斋豆
-
- 回帖
- 0
- 积分
- 101
- 在线时间
- 小时
- 注册时间
- 2010-10-7
- 最后登录
- 1970-1-1
|
Intern positions:
4 B& ^+ U& ? a r$ N+ I; b$ f4 L" c
' z9 u7 q: u& `3 J$ [9 Z* v5 AASIC Design/Verification Intern (Vacancy:3)
8 }8 j" }# q0 [6 `Job Description:
5 n- Q% u; ?( o4 w5 y2 Z# t1. Design/Verification of video surveillance and audio & voice processor with integrated CODEC and amplifier
2 [% k% Y2 s& F# r/ y; R: d$ P' S* ]2. Unit level & system level testbench build up with SystemC or OVM/UVM" ]2 H4 [+ m- ?
3. Bus Functional Models & APIs development6 V1 ?- I* _# {1 x4 |# M7 m- R8 v; I
4. Verification of AMBA-based DMA, DDR Memory Subsystem, and peripheral interfaces including PCIe, USB, SPI, BT656/BT1120, I2C, etc.9 G4 e* V/ P% j% G; z, U: U
5. High-quality verification with Code Coverage analysis and functional coverage analysis. Q" u! b1 o8 e: L, I! }0 K
6. Provide support to ATE/DFT and Validation
7 j4 z$ d4 K6 k) k" N. y5 [, B3 |' p7 w; Y
Job requirement:
' V8 z5 p- V1 j/ _7 F7 b; t7 W1. Majoring in Electrical Engineering, microelectronics or image/graphics processing is preferred
9 ^7 d/ {( o$ ]7 P, k2. Master C/C++ coding and verilog coding, systemC and SystemVerilog is preferred( U3 o, f0 k# H% l; @. ]( e% I/ t1 z
3. Strong DSP background is highly desirable3 k0 E7 B5 ?7 @# @1 G& K# G
4. Knowledge of video coding standard including H264 MPEG-4 is preferable.
0 a8 w8 l+ N& |2 h5. Knowledge of RTL design and verification
& ], p2 o0 ?; @1 h1 K6. Knowledge of Perl and Tcl scripting
9 A( Z5 w* ~1 z( E$ r7. Able to understand Verilog RTL code, debug simulation errors, identify and fix RTL/Environment issues: ~- B8 D L; t& {" ^+ k: T* B
8 S, i* w) _& s' ~' o; z
联系人:
\; k6 ?- U% x% k9 u* X卢先生& g% v! V m' Y
邮箱:lush123@sina.com
5 R& i O5 X, F k |
|