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- 2010-10-7
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Intern positions:# V" q9 i( n! b/ i
5 ?7 D* j f; R- V( u IASIC Design/Verification Intern (Vacancy:3)
8 Y; ]0 G1 t. H- Q$ G- z* mJob Description:
& F* P ]' J' G: o1. Design/Verification of video surveillance and audio & voice processor with integrated CODEC and amplifier
' w3 O) P" ^+ @6 Q2. Unit level & system level testbench build up with SystemC or OVM/UVM1 }" S: T$ m* }; ]+ Y- I) ]
3. Bus Functional Models & APIs development/ s" W& O$ w7 B4 X( x$ y: o# E
4. Verification of AMBA-based DMA, DDR Memory Subsystem, and peripheral interfaces including PCIe, USB, SPI, BT656/BT1120, I2C, etc.
( P( ?8 L5 h7 Z3 G& h5. High-quality verification with Code Coverage analysis and functional coverage analysis
8 m" }$ u: m9 j* u6. Provide support to ATE/DFT and Validation
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Job requirement: 8 m" z0 w7 I; `2 H) Y, E
1. Majoring in Electrical Engineering, microelectronics or image/graphics processing is preferred
* `- A: z6 G% r* M7 D2. Master C/C++ coding and verilog coding, systemC and SystemVerilog is preferred
: E- e# O% x" c7 v3. Strong DSP background is highly desirable' {5 J! v/ G3 C) b1 f8 _
4. Knowledge of video coding standard including H264 MPEG-4 is preferable.' k2 r9 X" g9 T9 @
5. Knowledge of RTL design and verification
& x" Q: L3 ^5 G6. Knowledge of Perl and Tcl scripting
; {; R& V5 U0 |4 h7. Able to understand Verilog RTL code, debug simulation errors, identify and fix RTL/Environment issues
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联系人: U0 U3 l; d5 _. j
卢先生
) Q5 h# V( w$ ?+ H7 a5 G邮箱:lush123@sina.com
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