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- 5262
- 斋米
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- 斋豆
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- 101
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- 2010-10-7
- 最后登录
- 1970-1-1
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Intern positions:
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" M( `/ c/ S6 |) MASIC Design/Verification Intern (Vacancy:3); ?" {$ `$ \+ ^/ H6 S7 f( @, X Z
Job Description:+ M/ b" A; r! q# D- `! G
1. Design/Verification of video surveillance and audio & voice processor with integrated CODEC and amplifier6 }5 F' A1 U: N+ A+ G
2. Unit level & system level testbench build up with SystemC or OVM/UVM, p: t8 J0 F2 F0 L5 o
3. Bus Functional Models & APIs development$ @+ {' Q) r z$ E$ A! z
4. Verification of AMBA-based DMA, DDR Memory Subsystem, and peripheral interfaces including PCIe, USB, SPI, BT656/BT1120, I2C, etc.
2 i2 d s7 h8 }4 r& o1 r5. High-quality verification with Code Coverage analysis and functional coverage analysis
6 N" p1 }3 j( M& {2 Y5 R/ \6. Provide support to ATE/DFT and Validation* H) X% \+ ?, {7 ]9 T
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Job requirement:
* r8 c" ^. z5 k% ~& Q1. Majoring in Electrical Engineering, microelectronics or image/graphics processing is preferred @1 n W2 h' d! V3 h0 ?. k
2. Master C/C++ coding and verilog coding, systemC and SystemVerilog is preferred
0 \/ o- f% Y5 {: f) e3. Strong DSP background is highly desirable
8 k9 ?2 E+ P& A: s }: J; t4. Knowledge of video coding standard including H264 MPEG-4 is preferable.2 s9 I, K* z, Y2 V, [
5. Knowledge of RTL design and verification
1 p3 l0 _. {+ G c4 i3 @3 P6. Knowledge of Perl and Tcl scripting 3 H! C$ ], W1 v* @# a; A H4 M: T
7. Able to understand Verilog RTL code, debug simulation errors, identify and fix RTL/Environment issues: U4 ?, `0 h) G
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联系人:1 h3 H. X2 P5 ]2 B. U
卢先生; [3 C. E' p; u* C4 [
邮箱:lush123@sina.com8 }( M5 C* |7 V* r5 p7 R% y
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