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凹凸科技(中国)有限公司成都分公司招聘实习生信息

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发表于 2012-2-29 19:54:48 | 显示全部楼层 |阅读模式
Intern positions:
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' z9 u7 q: u& `3 J$ [9 Z* v5 AASIC Design/Verification Intern (Vacancy:3)
8 }8 j" }# q0 [6 `Job Description:
5 n- Q% u; ?( o4 w5 y2 Z# t1. Design/Verification of video surveillance and audio & voice processor with integrated CODEC and amplifier
2 [% k% Y2 s& F# r/ y; R: d$ P' S* ]2. Unit level & system level testbench build up with SystemC or OVM/UVM" ]2 H4 [+ m- ?
3. Bus Functional Models & APIs development6 V1 ?- I* _# {1 x4 |# M7 m- R8 v; I
4. Verification of AMBA-based DMA, DDR Memory Subsystem, and peripheral interfaces including PCIe, USB, SPI, BT656/BT1120, I2C, etc.9 G4 e* V/ P% j% G; z, U: U
5. High-quality verification with Code Coverage analysis and functional coverage analysis. Q" u! b1 o8 e: L, I! }0 K
6. Provide support to ATE/DFT and Validation
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Job requirement:
' V8 z5 p- V1 j/ _7 F7 b; t7 W1. Majoring in Electrical Engineering, microelectronics or image/graphics processing is preferred
9 ^7 d/ {( o$ ]7 P, k2. Master C/C++ coding and verilog coding, systemC and SystemVerilog is preferred( U3 o, f0 k# H% l; @. ]( e% I/ t1 z
3. Strong DSP background is highly desirable3 k0 E7 B5 ?7 @# @1 G& K# G
4. Knowledge of video coding standard including H264 MPEG-4 is preferable.
0 a8 w8 l+ N& |2 h5. Knowledge of RTL design and verification
& ], p2 o0 ?; @1 h1 K6. Knowledge of Perl and Tcl scripting
9 A( Z5 w* ~1 z( E$ r7. Able to understand Verilog RTL code, debug simulation errors, identify and fix RTL/Environment issues: ~- B8 D  L; t& {" ^+ k: T* B
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联系人:
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邮箱:lush123@sina.com
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发表于 2012-2-29 22:21:54 | 显示全部楼层
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发表于 2012-2-29 22:39:54 | 显示全部楼层
介个和另一个帖子有什么区别么
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