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- 2010-10-7
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Intern positions:; |/ i/ F9 Y% e9 u+ W
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ASIC Design/Verification Intern (Vacancy:3). P" ~& i7 k- f) e" {' I# O/ c
Job Description:) v4 ^9 x+ S4 V9 ?' J
1. Design/Verification of video surveillance and audio & voice processor with integrated CODEC and amplifier K! p5 x5 p" Y. K0 Z
2. Unit level & system level testbench build up with SystemC or OVM/UVM- {0 i" n2 p7 u7 z7 H
3. Bus Functional Models & APIs development
5 e/ B5 \- g i, H+ H4. Verification of AMBA-based DMA, DDR Memory Subsystem, and peripheral interfaces including PCIe, USB, SPI, BT656/BT1120, I2C, etc.$ h8 @: b6 @9 h2 [1 k6 O4 z
5. High-quality verification with Code Coverage analysis and functional coverage analysis
9 A5 [. P O I1 R/ Q: v4 M+ ^5 t6. Provide support to ATE/DFT and Validation+ O3 H0 m( b' e1 l* B: F' A
$ U$ L$ _7 @; K& Z0 P9 sJob requirement:
1 `) Q( D) j& ^) d, b: ?5 W9 l1. Majoring in Electrical Engineering, microelectronics or image/graphics processing is preferred
1 [/ Y! {! g: r. \* v2. Master C/C++ coding and verilog coding, systemC and SystemVerilog is preferred
0 n3 C* S! Q p) v3. Strong DSP background is highly desirable
& }, }$ |% @$ T, H# \2 i9 H2 z4. Knowledge of video coding standard including H264 MPEG-4 is preferable.
* d+ x/ J6 ^$ Y5. Knowledge of RTL design and verification0 P/ R2 q. L( o7 ~3 @
6. Knowledge of Perl and Tcl scripting
0 C5 d3 P, I$ a9 _( l* s# v, x( M3 Z7. Able to understand Verilog RTL code, debug simulation errors, identify and fix RTL/Environment issues, r5 H9 a, K% \+ b" c
0 W8 l2 z, s6 y/ W联系人:' H8 s6 k' b1 ]7 Z: Y2 H
卢先生
+ V. l6 ^" P3 j1 ~7 ]邮箱:lush123@sina.com
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