Conexant 成都公司实习招聘

zl182005

Conexant  chengdu
$ t1 E& g% G; z* p0 W公司要招聘如下岗位的实习生
Intern positions:
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, i# a  G9 |8 X9 u3 Z% @ASIC Design/Verification Intern (Vacancy:3)
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Job Description:
1. Design/Verification of video surveillance and audio & voice processor with integrated CODEC and amplifier
3 j2 p" V* V8 I8 x2. Unit level & system level testbench build up with SystemC or OVM/UVM
3. Bus Functional Models & APIs development
4 y7 y& q" a0 E0 t+ x3 D" R/ X8 O( p4. Verification of AMBA-based DMA, DDR Memory Subsystem, and peripheral interfaces including PCIe, USB, SPI, BT656/BT1120, I2C, etc.
5. High-quality verification with Code Coverage analysis and functional coverage analysis
6. Provide support to ATE/DFT and Validation
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* P. v% I# y0 {# JJob requirement:
1. Majoring in Electrical Engineering, microelectronics or image/graphics processing is preferred
2. Master C/C++ coding and verilog coding, systemC and SystemVerilog is preferred
3 I& s% [) \: n% ^8 ?# u( {! [, A, ~3. Strong DSP background is highly desirable
% X" R6 T! O. {4. Knowledge of video coding standard including H264 MPEG-4 is preferable.
% ^) z7 |! M! \% u. Y6 B6 \  X+ H. d5. Knowledge of RTL design and verification
6. Knowledge of Perl and Tcl scripting
7. Able to understand Verilog RTL code, debug simulation errors, identify and fix RTL/Environment issues

& W- R" u% Y/ J# @. g: T* DJob requirement:
6 ]/ B; p2 t" E+ Z9 Q1. Majoring in Electrical Engineering, microelectronics or image/graphics processing is preferred
2. Master matlab is preferred
3. Master digital signal process
1 d- y  {5 w% d1 b% e5 T. \+ d8 P4. Master Runge-Kutta and math analysis
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  a( a' M$ a% W  [联系人：
卢先生
* ]8 M0 \  |7 |9 x8 l1 j请投简历至 邮箱：lush123@sina.com

+ N' L+ ]/ n3 V9 [- F' |! \可以2500/月以上

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