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- 斋米
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- 斋豆
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- 2012-2-29
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- 1970-1-1
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Chengdu Conexant Regular Full-time positions: / t! c6 }# S1 L1 V0 ^$ F, h6 Y- j
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SoC ASIC Design/Verification Engineer( Vacancy:1)
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5 \5 h' c; t) J) k7 _Job Responsibilities:9 k7 O- M: i+ Q) ]% t
1. Integration of ARM processor/DSP co-processor and AMBA bus for SoC;
3 N' }, W: i9 [5 \2. Integration of H264 Codec , DDR, USB and PCIe etc for SoC;" S. _; { ?5 r4 {
3. Design erification of video surveillance and audio & voice processor with integrated CODEC and amplifier
# T" X5 T- u, _# {4. Design SoC-level logic including clock, reset, and DFT;
& |. g7 H& P- O! K5. Verification of AMBA-based DMA, Memory Subsystem, and all peripheral interfaces at unit level and SoC level
- g3 _! n8 L$ E0 [" c" h5 i8 V# m6. Work with analog group and physical layout team on analog macro integration and synthesis/timing analysis.
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+ I, Q$ K* U( M/ ]8 q& I( AJob Requirements:
$ Y) R( W0 Y7 t0 X) }9 d" ?# U5 Z1. 5+ years experience on SoC design and integration;0 j! b& |/ a) A% j: I# k6 T& E l
2. Hand-on experience in ASIC flow;& ?8 u9 k0 C$ c3 R$ {
3. Experience of ARM/DSP/AMBA integration and/or verification;
% z5 O) n. ?; Y. q& Q% _4. Experience of DMA design and/or verification;, x" r: i) [; h* D
5. Experience of H264 Codec & DDR SoC integration and verification$ f0 U- X3 k/ {! S* d6 H$ e# m
6. Experience of video surveillance project design and verification2 } ]* v; C: G& u% D3 D: o
7. Experience of design erification for audio & voice processor with integrated Codec and amplifiers is a big plus
- B3 ]3 B8 R9 B# P2 S' s- ^; p8. Domain knowledge on Nand Flash Controller, USB, and PCIe is a plus
3 U& G! v, d/ C( ^+ H. F9. DFT (Memory BIST and scan) design background is a plus
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ASIC Verification Engineer( Vacancy:2)
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& z8 ? g% {& |' b7 ]: vJob Description:9 d$ n' E7 O9 T5 c! R' v0 E
1. Instrumental in the development of infrastructure for the validation of OVM/UVM-based architectures and the verification of ASIC hardware.8 x* f% c: I6 F+ ]' ~
2. Additional duties include the development of directed and random hardware verification environments, and the application of those environments to ASIC verification' m: |4 X' u' Q* X# U
3. Integration of VIP and functional verification agents in OVM/UVM verification environment to support coverage-driven verification E3 n2 \% _# ]' e% X
4. Understand and verify the functionality of a given design element within the context of the block, chip and overall system
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Job Requirements:
" N- T0 W- W/ `# s1. Extensive Verilog experience with SOC verification environments.4 ~( l0 g! Q% `: Q8 n% V G# j
2. Verification experience on digital signal processing for communication system.: ?( F) C. V- i1 E+ H
3. Experience developing bus functional models, monitors, scoreboards, generators, functional coverage models7 s L/ M' X. U
4. Experience with high level verification languages such as SystemC, SystemVerilog, OVM or VMM, Vera or Specman, and strong C++ programming background
/ r4 a+ f9 Z& I4 @7 B7 L* s5. Shell scripts and Tcl/Perl expertise, create runsim, lsf, regression management scripts
1 s/ \2 X& [4 h7 e1 j- k0 c6. Able to understand Verilog RTL code, debug simulation errors, identify and fix RTL/Environment issues9 a$ o5 Y# F8 s0 @$ G! j8 v6 {' c
7. Strong DSP background is highly desirable
5 [) b! f4 f+ Y& p' Z8. Experience on SD/HD/SDI video is a plus
6 G5 s H+ o, \, s* |9. H264 Codec design erification experienced is desired- @4 r+ j9 Y$ }4 k$ d' n
10. Experience of design erification for cable equalizer is preferred. f. s( L; W8 J5 Y, K
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Inter Algrithom Engineer( Vacancy:2)1 h; j/ I8 D3 t1 X/ |
Job requirement: - R: [/ Z6 [ v+ A* T
1. Majoring in Electrical Engineering, microelectronics or image/graphics processing is preferred
# h4 @9 y8 E+ w* Z" y; v5 t5 x2. Master matlab is preferred
( x1 @& b% k2 `3. Master digital signal process or Opencv
+ h y+ b: r+ o$ T& q4. Master and math analysis# F( R7 X3 |! Z; F
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4 t) m1 U4 I: }0 j联系人:卢先生/ D, R+ f- ]* B! C% d! c6 l$ w7 j
请投简历至 邮箱:lush123@sina.com* l, D% h/ H% E9 N: @
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