Conexant 成都公司招聘

zl182005

Chengdu Conexant Regular Full-time positions:
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SoC ASIC Design/Verification Engineer( Vacancy:1)

Job Responsibilities:
7 v# }/ Z) c: ^1 N/ N0 e1. Integration of ARM processor/DSP co-processor and AMBA bus for SoC;
2. Integration of H264 Codec , DDR, USB and PCIe etc for SoC;
& b; F$ Y9 ]$ }8 C' x# f+ |& R3. Design erification of video surveillance and audio & voice processor with integrated CODEC and amplifier
4. Design SoC-level logic including clock, reset, and DFT;
4 |8 Q& d+ d/ e2 i5. Verification of AMBA-based DMA, Memory Subsystem, and all peripheral interfaces at unit level and SoC level
, g; _9 U4 e1 w6. Work with analog group and physical layout team on analog macro integration and synthesis/timing analysis.
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Job Requirements:
) |; Y' i* \( Q* }; l/ ^1. 5+ years experience on SoC design and integration;
" i  t5 ]  v  W" t9 o2. Hand-on experience in ASIC flow;
; S+ p2 w1 X$ K0 n% ~3. Experience of ARM/DSP/AMBA integration and/or verification;
1 I" y6 R0 ]* I4. Experience of DMA design and/or verification;
/ Y# _* e4 A$ Y1 W9 F5. Experience of H264 Codec & DDR SoC integration and verification
; X* S& I- E' [, w6. Experience of video surveillance project design and verification
6 r: S7 D( m4 B0 h7. Experience of design erification for audio & voice processor with integrated Codec and amplifiers is a big plus
! K7 P& p) Y* O7 t4 N  G$ ~8. Domain knowledge on Nand Flash Controller, USB, and PCIe is a plus
9. DFT (Memory BIST and scan) design background is a plus

ASIC Verification Engineer( Vacancy:2)

Job Description:
1. Instrumental in the development of infrastructure for the validation of OVM/UVM-based architectures and the verification of ASIC hardware.
% l; r5 K2 B0 F/ m$ w) d0 L5 e2. Additional duties include the development of directed and random hardware verification environments, and the application of those environments to ASIC verification
6 ]2 b0 C( w+ a$ T3. Integration of VIP and functional verification agents in OVM/UVM verification environment to support coverage-driven verification
* p, ^+ M; g9 ?; P- Y9 A4. Understand and verify the functionality of a given design element within the context of the block, chip and overall system
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" ?, F+ s* P1 Y( TJob Requirements:
1. Extensive Verilog experience with SOC verification environments.
2. Verification experience on digital signal processing for communication system.
7 `+ z! W' \: w/ Z3. Experience developing bus functional models, monitors, scoreboards, generators, functional coverage models
4. Experience with high level verification languages such as SystemC, SystemVerilog, OVM or VMM, Vera or Specman, and strong C++ programming background
5. Shell scripts and Tcl/Perl expertise, create runsim, lsf, regression management scripts
6. Able to understand Verilog RTL code, debug simulation errors, identify and fix RTL/Environment issues
7. Strong DSP background is highly desirable
" c; @+ p6 H+ V! x0 R8. Experience on SD/HD/SDI video is a plus
7 |. N$ G/ e1 S% c: m" x0 k9. H264 Codec design erification experienced is desired
10. Experience of design erification for cable equalizer is preferred
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8 E% A/ ^4 w) W9 m$ MInter Algrithom Engineer( Vacancy:2)
Job requirement:
4 @1 t" z' z! W" a( i/ k1. Majoring in Electrical Engineering, microelectronics or image/graphics processing is preferred
2. Master matlab is preferred
) J6 f1 g& {8 g1 V3. Master digital signal process or Opencv
4. Master and math analysis
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/ u) m% T5 T5 G# J9 k联系人：卢先生
3 d" v8 j3 m: z8 Y8 j请投简历至 邮箱：lush123@sina.com
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