Conexant 成都公司招聘

zl182005

Chengdu Conexant Regular Full-time positions:
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. a  \6 G2 M- i# d) f3 L3 \SoC ASIC Design/Verification Engineer( Vacancy:1)

7 E: }  t  e5 wJob Responsibilities:
1. Integration of ARM processor/DSP co-processor and AMBA bus for SoC;
2. Integration of H264 Codec , DDR, USB and PCIe etc for SoC;
; Q5 {6 ?  [. S2 t* l5 r  K: v3. Design erification of video surveillance and audio & voice processor with integrated CODEC and amplifier
" M6 l$ }# C* ^( B5 q! V, y4. Design SoC-level logic including clock, reset, and DFT;
5. Verification of AMBA-based DMA, Memory Subsystem, and all peripheral interfaces at unit level and SoC level
% v- r) o1 e5 a6. Work with analog group and physical layout team on analog macro integration and synthesis/timing analysis.

6 ?# @) B- B; X7 Q. G+ v* [Job Requirements:
. `2 W! X( k4 ^! i! W1. 5+ years experience on SoC design and integration;
2. Hand-on experience in ASIC flow;
$ l! J8 {% d- m+ V) k) k3. Experience of ARM/DSP/AMBA integration and/or verification;
* W/ n6 i; [+ c- L4. Experience of DMA design and/or verification;
$ m2 l  k5 p5 f6 P  Y5. Experience of H264 Codec & DDR SoC integration and verification
6. Experience of video surveillance project design and verification
7. Experience of design erification for audio & voice processor with integrated Codec and amplifiers is a big plus
3 W$ l. O6 v8 [' _0 A* c$ l8. Domain knowledge on Nand Flash Controller, USB, and PCIe is a plus
9. DFT (Memory BIST and scan) design background is a plus

ASIC Verification Engineer( Vacancy:2)

Job Description:
1. Instrumental in the development of infrastructure for the validation of OVM/UVM-based architectures and the verification of ASIC hardware.
2. Additional duties include the development of directed and random hardware verification environments, and the application of those environments to ASIC verification
" s+ h+ R- j0 S3 h+ p3 n4 D3. Integration of VIP and functional verification agents in OVM/UVM verification environment to support coverage-driven verification
4. Understand and verify the functionality of a given design element within the context of the block, chip and overall system

' S  J5 w! }% j8 I0 _0 gJob Requirements:
1. Extensive Verilog experience with SOC verification environments.
2. Verification experience on digital signal processing for communication system.
2 x5 v+ p  P: l. b! D; k' V3. Experience developing bus functional models, monitors, scoreboards, generators, functional coverage models
! S/ h8 K0 a+ [) ^$ t4. Experience with high level verification languages such as SystemC, SystemVerilog, OVM or VMM, Vera or Specman, and strong C++ programming background
8 O6 s. I7 C) E7 F% h0 @5. Shell scripts and Tcl/Perl expertise, create runsim, lsf, regression management scripts
6. Able to understand Verilog RTL code, debug simulation errors, identify and fix RTL/Environment issues
7 n  ~* y: q1 d: T4 ^6 Q6 R0 {7. Strong DSP background is highly desirable
8. Experience on SD/HD/SDI video is a plus
9. H264 Codec design erification experienced is desired
10. Experience of design erification for cable equalizer is preferred

Inter Algrithom Engineer( Vacancy:2)
Job requirement:
- x0 {' W6 Y1 R  S1. Majoring in Electrical Engineering, microelectronics or image/graphics processing is preferred
2. Master matlab is preferred
3. Master digital signal process or Opencv
$ Y! X/ e- ~* u9 }: `0 h2 f4. Master and math analysis
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联系人：卢先生
0 i7 Z, f2 Z. j6 ^+ z- x& u* P3 u请投简历至 邮箱：lush123@sina.com
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li3891419

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