Conexant 成都公司招聘

zl182005

Chengdu Conexant Regular Full-time positions:
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SoC ASIC Design/Verification Engineer( Vacancy:1)

6 B9 e3 @' ^( c6 u: K( jJob Responsibilities:
" U' V7 }, {2 E/ l9 T, [; e1. Integration of ARM processor/DSP co-processor and AMBA bus for SoC;
, ]* `' I0 N: L+ |2. Integration of H264 Codec , DDR, USB and PCIe etc for SoC;
3. Design erification of video surveillance and audio & voice processor with integrated CODEC and amplifier
4. Design SoC-level logic including clock, reset, and DFT;
9 t$ ]; _( b/ I2 ^2 Y7 Y5. Verification of AMBA-based DMA, Memory Subsystem, and all peripheral interfaces at unit level and SoC level
6. Work with analog group and physical layout team on analog macro integration and synthesis/timing analysis.
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' X) u1 X; H. W0 W% P, K5 n0 zJob Requirements:
4 D7 A) x9 r+ G7 v& C1. 5+ years experience on SoC design and integration;
2. Hand-on experience in ASIC flow;
3. Experience of ARM/DSP/AMBA integration and/or verification;
# @. h& T5 n# x" s" j9 g2 g7 o* x* X& L" Z4. Experience of DMA design and/or verification;
5. Experience of H264 Codec & DDR SoC integration and verification
& X0 [2 e2 `: w& H( g; L2 |6. Experience of video surveillance project design and verification
7. Experience of design erification for audio & voice processor with integrated Codec and amplifiers is a big plus
8. Domain knowledge on Nand Flash Controller, USB, and PCIe is a plus
9. DFT (Memory BIST and scan) design background is a plus

6 [" W5 G# T. V& ?ASIC Verification Engineer( Vacancy:2)

$ H( J: K- E7 f# @/ P+ O( y% u& gJob Description:
1. Instrumental in the development of infrastructure for the validation of OVM/UVM-based architectures and the verification of ASIC hardware.
1 t# t& ?+ I6 }) s, P% A" h% F2. Additional duties include the development of directed and random hardware verification environments, and the application of those environments to ASIC verification
3. Integration of VIP and functional verification agents in OVM/UVM verification environment to support coverage-driven verification
7 ^* ^, [. q' |( F1 C4. Understand and verify the functionality of a given design element within the context of the block, chip and overall system

9 i5 C8 b. o; K- I% XJob Requirements:
, _' x# O8 d8 J- x$ \) x$ Q4 Q1. Extensive Verilog experience with SOC verification environments.
% ]" `* O; L% Z; b; X; d  m  r2 Q2. Verification experience on digital signal processing for communication system.
3. Experience developing bus functional models, monitors, scoreboards, generators, functional coverage models
4. Experience with high level verification languages such as SystemC, SystemVerilog, OVM or VMM, Vera or Specman, and strong C++ programming background
# x8 e. a' Y0 p  J/ e4 E5. Shell scripts and Tcl/Perl expertise, create runsim, lsf, regression management scripts
6. Able to understand Verilog RTL code, debug simulation errors, identify and fix RTL/Environment issues
7. Strong DSP background is highly desirable
  |1 B& N, a9 \- E8. Experience on SD/HD/SDI video is a plus
! l1 _2 h7 C0 W( l! V. @' J% B: o9. H264 Codec design erification experienced is desired
10. Experience of design erification for cable equalizer is preferred

, U1 V) N* L  {5 n$ _+ Y  ]Inter Algrithom Engineer( Vacancy:2)
( S1 e* _$ y) [5 ]9 lJob requirement:
1. Majoring in Electrical Engineering, microelectronics or image/graphics processing is preferred
) Z4 x9 d/ @  R( k2 `, h/ [3 V2. Master matlab is preferred
3. Master digital signal process or Opencv
- g/ C' a! x8 i! ~& N5 t( [4. Master and math analysis


联系人：卢先生
6 a$ y- Q2 g* g* k! d请投简历至 邮箱：lush123@sina.com

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