【实习】NVIDIA 英伟达实习生招聘

nvidiahr

有兴趣的同学，将简历投递至harryf@nvidia.com 所有职位都是base在上海
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4 l" _4 r( v& C- k6 GASIC Intern
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Job Description/Qualifications:
2 u9 C6 N. E3 L0 L% J# t6 X8 s( ^- BS/MS in electrical/computer engineering and related.
2 z" f7 [" O' m* A5 a' Q9 y' e. ^- Good skills in Verilog. Solid understanding in RTL sim verification of digital design.
- Perl scripting skills is appreciated as a plus.
$ o" a9 i+ f0 K1 t0 P- Fluent English (both written and spoken) and excellent communication skills
7 j3 s0 Q+ _. g8 I- Demonstrated ability to work independently as well as in a multi-disciplinary group environment
* i8 _6 |+ N1 p0 ?" i______________________________________________________________________________
7 k  b& r2 H" BASIC design/verification intern

Job Description/Qualifications:
- BS/MS in electrical/computer engineering and related.
2 M: d& N* A* y9 S7 a4 h8 J- Good skills in Verilog. Solid understanding in RTL sim verification of digital design.
- Perl scripting skills is appreciated as a plus.
- Database/Web design experience is appreciated as strong plus.
- Fluent English (both written and spoken) and excellent communication skills
6 {: o2 Z) l% b0 D/ V. C: G- Demonstrated ability to work independently as well as in a multi-disciplinary group environment
0 G; z% o" Q+ h7 q, ?______________________________________________________________________________
ASIC Intern

Job Description/Qualifications:
! }. k2 q# ~, F8 f& @2 z  B8 b- Maintain regression suit, triage failing tests
- Improve wiki page and user documents
- Maintain infrastructure and tree
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( P* `# |$ v' {# b! k& ]" bPhysical Design Engineer
4 z2 k& a* {( L2 V: M$ CResponsible for flow automation, regression test.
Analysis on placement, routing, timing, clock, power, noise and DFM.
: s' j2 s! ~' y6 e8 ^On-demand testing support and infrastructure coding in perl/tcl/makefile/java.

  E. @" H$ P# i2 C. QMinimum Requirement:
; \, |3 w8 q' m; r9 {MSEE
6 W; Q7 v) e: M1 l8 |& G, zBasic knowledge of device model, processing technology, timing, noise and power in chip design.
Proficient user of Perl or TCL ( or C, Python) is preferred.
Hands-on experience in EDA software from Synopsys (PC/ICC/DC/PT/STAR-RC), Cadence (First Encounter) is a plus.
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: r2 ^1 o) C( o& K$ M3 K/ tSystem Design Engineer - GPU Arch
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/ B; f! D2 i% m( {$ i; c# vJob Description/Qualifications:
) X: N) P9 e, N8 dResponsibilities:
- We are looking for world class engineers to design, model, analyze and verify next generations of GPU architecture.
9 P- ~1 f# K# X- The candidates will work with a group of architects to design and develop proprietary internal tools for the visualization, analysis, and debug and verification of tests and applications on various functional and performance simulations of future chips.
1 S, N& [+ h: R3 u9 @- The candidates will have opportunities to get involved in cutting-edge GPU macro- and micro-architecture design, verification and optimization, including porting commercial applications to test benches, identifying performance hotspots and data mining for performance analysis.
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( F# R! ^5 [: i9 t, }! f* r. E" z& jRequirements:
- Bachelor Degree or higher majoring in CS/EE/Mathematics or relevant fields.
' ]5 O7 n/ j; e7 t- Solid computer science background
- Strong C/C++ programming ability.
- Excellent English writing for engineering documentation, English oral well enough to attend meetings.
- Experience in the following areas is a plus:
. Q# }& w4 z3 ?( f& V6 P) [- Scripting language (Perl, Python, Ruby) experience is a plus.
- 3D graphics (D3D or OpenGL) application development.
- Parallel computing/CUDA/OpenCL/HPC development.
- Microprocessor architecture design & verification.
- System level programming experience in OS, compiler, driver, tools, virtual memory system, etc.
- Multimedia (video, image processing, visualization) application development
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Developer Tools QA software  engineer
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8 J7 |1 x. [! L- m3 f  r3 \Job Description/Qualifications:
( S, Z5 Q7 z2 T- |2 R' I: NQualifications: The candidate will take the responsibility to test our software distributions that includes mobile/embedded OS, SDK, compilers and samples codes.
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1 G7 S: A) F3 r/ u9 K7 F8 o- Strong knowledge on Windows and Linux Operating systems
/ B, H( M. C: Y+ R+ o- Knowledge on build tools like Make and ant
- Strong at scripting, like perl , shell and batch scripting.
- Good debugging skills and analysis skills on installations and builds
5 ^4 \8 h2 ~0 e$ |" B- R- Good hands on about Strong analysis skills on system / product configurations and setups.
- Added advantage with C,C++
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, d+ v9 v) b0 ]0 tPower ASIC Engineer Intern

6 B- P; s! c) `3 @7 ePower methodology team is responsible for researching power expenditures and workload efficiency to identify architectural, micro-architectural strategies to improve power efficiency of the next generation GPU and TEGRA chips.
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Responsibilities:
( W# B& X8 \# a7 i5 m) f: IDevelop the power flow to automate the power expenditures measurement.
! T- p! A# g" V7 w6 OEvaluate new low-power technologies and provide feedback to power ARCH team to improve chip power efficiency on architectural level.
2 s  T( o& V+ _4 ASupport GPU/TEGRA RTL designers using the power flow to do the power scrubbing work and improve their power efficiency on micro-arch level.
Understand and perform block level and chip-level power analysis.

) T% I' U0 D6 l: ]  ORequirements:
6 x  m7 b- b$ `  cExperience on ASIC related areas like ASIC design/verification.
Knowledge on advanced low power techniques and high speed clocking desired.
' r( K: z- c* V( \$ u4 yKnowledge on low power ASIC design/verification.
Programming languages: Strong Verilog (or VHDL), Perl, Tcl is must,  C ++ is a plus.
Tool Familiarity: PTPX, Synopsys Design Compiler, VCS simulation tool is must, Power Artist is a plus.
% r  D# U6 Q, j$ D- R9 t: a; ?Excellent communication skills and ability to be good at teamwork.
Excellent English writing/speaking skills.
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# V" _/ |3 s  s8 K8 s! XCompute Architect Intern
2 d1 Q/ V% i+ J; \. O% k) \Job Description/Qualifications:
The NVIDIA GPU Computing Architecture group is seeking intern candidates with backgrounds in computer architecture and compute science to join our effort to advance the state of parallel computing.
Our team is designing the fastest and most efficient parallel architectures that power energy-efficient smart phones and the world's fastest super computers.
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RESPONSIBILITIES:
Develop innovative HW, DSP, GPU and system architectures to extend the state of the art in performance, programmability, efficiency and reliability
/ X- M4 I4 ^& k! KAnalyze and prototype key algorithms for new GPU architectures
Collaborate across the company to guide the direction of GPU computing, working with software, research and product teams
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DESIRED SKILLS and EXPERIENCE:
MS Degree in relevant discipline (CS, EE, Math). PhD helpful
# L; \, K9 a5 Z- `* ?Strong programming skills in C or C++
- X9 ]7 _0 l) v" T4 Q$ P' oStrong background in computer architecture, compilers, parallel processing, signal processing and/or high performance computing
(optional) Strong programming skills in CUDA, Perl, OpenMP, MPI or Python is big plus
(optional) Experience in computer vision, machine learning, and molecular dynamics is big plus
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4 @$ x  b0 j- C) ZCUDA AUTOMATION TRIAGE QA ENGINEER

% y, T7 O$ t) s$ J& N( v3 f1 FRESPONSIBILITIES:
* G( N; d1 U. e, y9 j+ y- GPU Computing test with CUDA to ensure functionality, compatibility and performance.
  @) S( X( B2 \- Test staging area cuda enabled display driver and CUDA toolkit.
. ?5 p" s: ^4 I5 q- Report and analyze the nightly failures from CUDA nightly testing.
; L8 p7 Q3 }6 Y( j" L- Maintain and fix bug for CUDA nightly testing configuration files.
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! x. c, K% U- k+ g$ q) aMINIMUM QUALIFICATIONS:
- A good degree from a leading university in an engineering or computer science related discipline (BS; MS or PhD preferred).
: ~, A5 g1 `" u* W% B. I( `- Familiar with Linux and Windows operating systems.
5 l6 L5 r( d1 j! Y& l& C: L! V- Be good at C/C++ and python programming a plus.
- Good trouble shooting, analytical skill, logical thinking and inferences capability a must.
- Excellent English communication and collaboration skills.
- Ability to work independently and achieve results on tight time lines.

  ]: E( F2 l% K* c* ~DFT Intern

! `/ L& D/ t4 m. C9 ]2 N( Y4 qResponsibilities:
•        Responsible for DFT logic verifications including analog, jtag, mbist or other DFT features.
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# |: l( p  r0 S+ G0 g  @- KMinimum Requirement:
•        Master students who will be graduating in 2017.
! ^4 O, s2 K, N6 E: {3 r/ |•        Strong logic Design and verification background.
•        Good at Verilog coding and familiar with simulation tools.
•        Must possess a basic knowledge of DFT including scan, ATPG, JTAG and BIST.
•        Programming in Perl, tcl and C/C++ is a plus
•        Good English communication skills
) @" L$ d/ o4 k( y% W8 f•        Good problem solving skills
; L! P9 Y2 k! L3 r5 o1 m8 N1 v  `) \•        Self-motivated and good team player
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