10K-20K 上海 应届毕业生 硕士及以上 全职 职位诱惑: 顶尖技术 Design Engineer · position description Candidates will beinvolved in the whole ASIC design flow from RTL coding through P&R support,which includes logic design, DFT planning and implementation, logic synthesis,power optimization, static timing analysis and sign-off. Candidates will alsowork closely with analog design teams on IP integration, with P&R engineerson chip floor planning and timing optimization, and with product/test engineerson ATE tests. · Job Description Work closely withfrontend and backend design teams, as well as test engineers. Participatein logic design for some timing critical blocks in SOHO switch/PHY chips andASICs. Perform logic synthesis, floor planning, timing analysis and timingsignoff for chip tapeout. Work on DFT designs including MBIST, EDT, OCC, JTAG.Run Mentor and Synopsys tools to create and verify ATPG patterns. Work withtest engineers to build up and debug test programs. · Job qualification · MSEE degree* K2 W* h( F+ \( P, u/ M9 T
· 0~2 years of hand-on experience in digital design, running EDAtools of simulation, synthesis, timing analysis and formalverification
3 h7 [0 ^) Q8 P8 O& @· Solid knowledge and background in ASIC development
+ i/ E, g9 ]' y Good communication skills 详情请扫描下方二维码: - z! }6 T/ Y+ s. s# r( s' U) e
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