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【Intel】Yield Integrator

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发表于 2017-3-25 21:13:04 | 显示全部楼层 |阅读模式
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Location: Chengdu( Z2 h6 j4 E3 m6 @
Contact: saw.yen.yew@intel.com, m3 m* C. [  ^: \
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Description7 _9 A  _2 {+ p
Process Yield Integrator is responsible for monitoring whole line Process Induced Yield Loss, finding root cause and navigating process improvement plan.. W; F' w0 P- }# R' u* z8 ?  @
Your responsibilities will include but not be limited to 3 O! {; r: K+ [, U( t, Y
-Identifying the yield improvement opportunities through Modular Based Problem Solving and managing the yield improvement roadmap. 6 `/ P  [" M6 p) f& Z) p
-Working closely with Technology Development Team/Die Prepare manufacturing/Module/Manufacturing/Material to identify and fix the causes of yield loss
7 C% a' A3 a0 r" F-Actively engage excursion management
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Qualifications
! n7 _; H0 P8 V" t4 K: p0 rYou must possess a Master or Bachelor degree in engineering background; Additional qualifications include: $ t+ W6 }% Y5 P2 r
-A good understanding on Assembly/Test process, PCS, Excursion Management, Data Extraction and Data Analysis Tools. : Z( J# q2 E) }$ Y6 b. }8 {
-Demonstrated strong problem-solving skills
) w5 v' ~8 C! J2 t& d! H8 l-Good analytical capabilities as well as a solid teamwork orientation and outstanding communication skills
3 o0 p. S" T4 w' ~' u" g1 k  M-Self-motivated, reliable to deliver on time, a quick-thinker, be able to work in a fast-paced work environment - j* S0 a) U: J/ K. v2 T+ V
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This is a full time college graduate position. It’s suitable for student who is going graduated in Y16 or Y17.3 R& e: O. t5 k* j+ l. {
Please subject your email as ‘Yield Integrator_Chengdu’ when applying to saw.yen.yew@intel.com
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